The present invention is related in general to the field of semiconductor devices and processes and more specifically to structure, materials and fabrication of high-performance, high I/O solder-attached and ball grid array packages.
Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input/output (I/O) count. BGA packages use sturdy solder balls for surface mount connection to the xe2x80x9coutside worldxe2x80x9d (typically plastic circuit boards, PCB) rather sensitive package leads, as in Quad Flat Packs (QFP), Small Outline Packages (SOP), or Tape Carrier Packages (TCP). Some BGA advantages include ease of assembly, use of surface mount process, low failure rate in PCB attach, economic use of board area, and robustness under environmental stress. The latter used to be true only for ceramic BGA packages, but has been validated in the last few years even for plastic BGAs. From the standpoint of high quality and reliability in PCB attach, BGA packages lend themselves much more readily to a six-sigma failure rate fabrication strategy than conventional devices with leads to be soldered.
A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for improved thermal performance during device operation, necessary for consistently good electrical performance. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
One of the substrate layers includes a signal xe2x80x9cplanexe2x80x9d that provides various signal lines, which can be coupled, on one end, to a corresponding chip bond pad using a wire bond (or to a contact pad using flip-chip solder connection). On the other end, the signal lines are coupled with solder xe2x80x9cballsxe2x80x9d to other circuitry, generally through a PCB. These solder balls form the array referred to in a BGA. Additionally, a ground plane will generally be included on one of the substrate layers to serve as an active ground plane to improve overall device performance by lowering the inductance, providing controlled impedance, and reducing cross talk. These features become the more important the higher the BGA pin count is.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in reliability characteristics such as insensitivity to temperature cycling or moisture environment. BGA packages suffer from the drawback that, in operation and temperature excursions, they are sensitive to thermomechanical stress due to the mismatch between the coefficients of thermal expansion of the semiconductor material and the printed circuit board material.
These reliability risks, as well as the requirements for special pad metallizations, have been described in a series of detailed publications by the International Business Machines Corporation in 1969 (IBM J. Res. Develop., Vol. 13, pp. 226-296): P. A. Totta et al., SLT Device Metallurgy and its Monolithic Extension, L. F. Miller, Controlled Collapse Reflow Chip Joining, L. S. Goldmann, Geometric Optimization of Controlled Collapse Interconnections, K. C. Norris et al., Reliability of Controlled Collapse Interconnections, S. Oktay, Parametric Study of Temperature Profiles in Chips Joined by Controlled Collapse Techniques, B. S. Berry et al., Studies of the SLT Chip Terminal Metallurgy.
During actual BGA operation, significant temperature differences and temperature cycles between semiconductor chip and substrate will appear. Consequently, the reliability of the assembly is strongly influenced by the coefficients of thermal expansion of the semiconductor and the substrate. For example, there is more than one order of magnitude difference between the coefficients of thermal expansion of silicon and FR-4. This difference causes thermomechanical stresses which the solder joints have to absorb. Detailed calculations, in the literature references cited above and in others, of the optimum height and volume of the solder joint and the expected onset of thermal fatigue and cracking showed that it is desirable to have
a highly ductile solder;
a high ultimate shear strength of the chip/joint and substrate/joint interfaces;
a large value for the ratio (radius of bump-to-chip contact)/(distance to neutral point of chip). With the ongoing trend to increase chip sizes and to reduce area consumption for bonding pads, both driven by cost reduction efforts, the latter goal is obtained ever less and has to substituted by other improvements.
One method aims at absorbing part of the thermomechanical stress on the solder joints by plastic material surrounding the joints and filling the gap between chip and substrate (designated 15 in FIG. 1). See for instance, U.S. patent applications Ser. Nos. 60/084,416, 60/084,440, and 60/084,472, filed May. 6, 1998 (Thomas et al., Low Stress Method and Apparatus of Underfilling Flip-Chip Electronic Devices). However, this method is expensive, because it represents an additional process step, and it may not be welcome since the customer may have to perform the process after device attachment to the motherboard.
Another method aims at intentionally sacrificing solder joints located in extreme locations (for instance, in chip corners) where the stress is highest, in order to save the majority of joints from failure. However, this method consumes valuable semiconductor real estate and it thus expensive; it is generally more a defense against the problem than an avoidance of the problem.
Another method aims at designing electrical redundancy of chip input/output terminals; see for instance U.S. patent application Ser. No. 60/080,122, filed Mar. 31, 1998 (Ibnabdeljalil et al., Electrical Redundancy for Improved Mechanical Reliability in Ball Grid Array Packages). However, this method consumes valuable input/output terminals and semiconductor real estate, and is thus expensive; it is generally more a defense against the problem than an avoidance of the problem.
An urgent need has therefore arisen for a coherent, low-cost method of fabricating BGAs and assemblies of semiconductor devices on circuit boards offering a fundamental solution for thermomechanical stress reliability. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, should allow the usage of various formulations of substrate material, and should achieve improvements toward the goal of small outline and low profile packages. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
According to the present invention, the thermo-mechanical stress sensitivity of ball grid array (BGA) solder connections is eliminated, when the solder connections solidify in column-like contours after reflowxe2x80x94a result achieved by using the solder material in tapered openings of a thick sheet-like elastic polymer adhered to the BGA substrate and selected for its characteristics of non-wettability to solder and volumetric shrinkage greater than solder.
The present invention relates to high density, high speed integrated circuits in ball grid array packages and to packages which have an outline similar to the integrated circuit chip itself. It also applies to chips with solder balls assembled by flip technology. These circuits can be found in many device families such as processors, digital and analog devices, memory and most logic devices, high frequency and high power devices, especially in large chip area categories. The invention helps to alleviate the space constraints in continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrumentation.
It is an aspect of the present invention to be applicable to a variety of different semiconductor solder-ball-assembled package designs; for example, the chips may be assembled by wire bonding and overmolding, or by a flip-chip process with or without underfilling. A variety of substrate designs or stacks of metal-insulator layers may be used.
Another aspect of the invention is to utilize existing semiconductor fabrication processes and to reach the assembly goals without the cost of equipment changes and new capital investment, by using the installed fabrication equipment.
Another aspect of the invention is to be applicable to a variety of different solder ball sizes and compositions, as long as the polymer tape is not wettable by the selected solder and has a higher volumetric shrinkage than the selected solder.
These aspects have been achieved by the teachings of the invention concerning methods suitable for mass production. Various modifications have been employed for the assembly of semiconductor chips and insulating substrates.
In one embodiment of the invention, an interconnection substrate comprises an electrically insulating support, having a plurality of contact pads disposed on its surface, and a sheet-like elastic polymer, non-wettable by solder and having a coefficient of volumetric shrinkage greater than solder, adhering to the support. Openings in the polymer sheet expose the contact pads. After solder connections are reflowed onto the contact pads, without wetting the walls of the opening, the cooling cycle creates column-like contours of the solidifying solder as well as a gap between the solder and the walls, due to the volumetric shrinkage of the polymer. The resulting column-like solder connections have sufficient length after board attach to act as stress-distributing joints.
In another embodiment of the invention, complete semiconductor BGA devices are assembled using substrates with the thick and solder non-wettable sheet-like elastic polymer adherent to the substrate surface. Again, column-like solder connections are formed in the cooling cycle after the reflow process.
In yet another embodiment of the invention, the thick and solder non-wettable sheet-like elastic polymer is attached to the semi-finished semiconductor package in a sort of xe2x80x9cretrofitxe2x80x9d before the solder balls are attached. By this method, existing devices can be xe2x80x9cupgradedxe2x80x9d to obtain, upon completion of the solder reflow cycle, the feature of stress-insensitive solder connections.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.